Reactance adjustment device, transceiver and transmission device using the same, signal processing circuit suitable for them, reactance adjustment method, transmission method, and reception method

ABSTRACT

A reactance adjuster includes an electrode ( 123 ) inducing an electric-field in an electric-field transmittable medium ( 121 ), an adjusting signal generation section ( 13 ) outputting alternatingly a high level or a low level signal to a resonance section ( 7 ), an electric-field detection section ( 15 ) generating an electric signal based on the electric-field in the medium ( 121 ), a first electric-charge storing means (C 1 ) storing electric-charge according to the electric signal when the section ( 13 ) outputs a high level signal, a second electric-charge storing means (C 2 ) storing electric-charge according to the electric signal when the section ( 13 ) outputs a low level signal, a voltage comparator ( 10 ) outputting a predetermined signal based on a voltage difference between the storing means, a control section ( 19 ) outputting a constant voltage when the first and the second storing means (C 1,  C 2 ) are storing electric-charge and a voltage based on a predetermined signal when the storing ends.

TECHNICAL FIELD

The present invention relates to a reactance adjuster that adjustsreactance caused by an electric field transmittable medium and acommunication apparatus for transmitting and/or receiving a signalincluding data to be transmitted or received via the electric fieldtransmittable medium, a transmitter and a transceiver using thereactance adjuster, and a signal processing circuit preferable to these.Moreover, the present invention relates to a reactance adjusting method,a transmitting method, and a receiving method.

BACKGROUND ART

Due to a miniaturization and technological advancement of a mobiledevice, a wearable computer mountable to a living body has attracted alot of attention. In the past, as data communications between suchwearable computers, there is proposed a method in which a transceiver isconnected to a computer and an electric field induced in the living bodyas an electric field transmittable medium by the transceiver istransmitted therein to transmit and receive data, for example, inJapanese Patent Application Laid-open Publication 2001-352298.

In an intra-body communication in which the electric field based on asignal including data to be transmitted and received is induced in theliving body and communications are carried out by detecting the inducedelectric field, when a transceiver that is not coupledelectro-statically with the earth ground is used, a favorablecommunication condition is realized by providing a variable reactancesection between a modulation circuit and a transmitting-and-receivingelectrode as shown in FIG. 1, by controlling the reactance value, andthus by increasing the electric field intensity induced in the livingbody.

FIG. 1 illustrates an example of a configuration of a transceiver usedin the intra-body communication. Referring to FIG. 1, the transceiver iscomposed of an oscillator 125 outputting an alternating signal as acarrier, a modulation circuit 101 modulating the carrier using data tobe transmitted, a switch 102 turning off at the time of adjustingreactance and transmitting or turning on at the time of receiving, avariable reactance section 106 causing resonance with parasiticcapacitances between a living body 121 and the earth ground and alsobetween a ground of the transceiver circuit and the earth ground, aswitch 103 turning on when detecting an electric field amplitude at thetime of a reactance value being large during reactance adjustment orotherwise turning off, a switch 104 turning on when detecting anelectric field amplitude at the time of a reactance value being smallduring reactance adjustment or otherwise turning off, a filter 108 and adetector 107 detecting an electric field amplitude at the time of areactance value being large, a filter 110 and a detector 109 detectingan electric field amplitude at the time of a reactance value beingsmall, a differential amplifier 111 obtaining a difference between theamplitudes at the time of the reactance value being large and small, anintegrator 112 integrating an output signal of the differentialamplifier 111 to output a control signal for controlling reactance, aswitch 105 allowing the integrator 112 to input the signal from thedifferential amplifier 111 during reactance adjustment and to input anelectric signal from a constant voltage source 113 during transmission,the constant voltage source 113 outputting the electric signal having avoltage value of zero to the integrator 112, an adjusting signal source114 outputting an adjusting signal for use in reactance adjustment, anadder 115 adding the adjusting signal to the control signal andoutputting to the variable reactance section 106, an electric fielddetection optical section 116 converting an electric field induced inthe living body into an electric signal, a signal processing section 117amplifying an output signal from the electric field detection opticalsection 116 and performing noise elimination or the like by a filter, ademodulation circuit 118 demodulating a received signal, a waveformshaper 119 shaping a waveform, switch 120 allowing the switches 103 and104 to input an output signal from the signal processing section 117 tothe switches 103 and 104 during reactance adjustment or transmission andthe demodulation circuit 118 to input the output signal duringreceiving, an input/output (I/O) circuit 122, atransmitting-and-receiving electrode 123, and an insulator 124.

In the transceiver having the above configuration shown in FIG. 1, areactance value of the variable reactance is controlled so as tomaximize an electric field to be induced in the living body 121. In thiscontrol, a reactance value is changed timewise from the reactance valueset by a control signal. The control signal is changed to be larger whenthe electric field amplitude at the time of a reactance value beinglarge is larger and to be smaller when the electric field amplitude issmaller. This operation continues to control until the amplitude becomesequal.

In FIG. 1, the electric field amplitude at the time of a reactance valuebeing large is detected by a circuit on the switch 103 side and theelectric field amplitude at the time of a reactance value being small isdetected by a circuit on the switch 104 side. These values are comparedby the differential amplifier 111. When the electric field amplitude atthe time of a reactance value being large is larger, a positive signalis inputted to the integrator 112, thereby increasing the control signaland reducing the reactance value. When smaller, a negative signal isinputted to the integrator 112, thereby reducing the reactance value. Inthis method, when a magnitude relation between the adjusting signal andreactance value is correct, the reactance is automatically controlled tobe the maximum.

In order to explain in detail, a waveform outputted from each componentillustrated in FIG. 2A and a change of the reactance value illustratedin FIG. 2B are referred to. B1 and C1 in FIG. 2B correspond to areactance value at the time of the adjusting signal B1 and C1,respectively. A1 is a reactance value at the beginning. In theconfiguration shown in FIG. 1, while the electric field amplitude isbeing detected, a signal is inputted to the integrator 112. When achange of the control signal is smaller than the amplitude of theadjusting signal, the reactance value at the time of C1 moves close tothe reactance value at the time of A1 but is still lower than thereactance value at the time of B1. Because a relation between theadjusting signal and the reactance value is not changed, a reactancecontrol is performed without any problem.

A waveform outputted from each component and a change in a reactancevalue when a change of the control signal is larger than the adjustingsignal are illustrated in FIGS. 3A and 3B, respectively. B2 and C2 inFIG. 3B are a reactance value when the adjusting signals in FIG. 3A areat B2 and C2, respectively.

In addition, as the integrator 112, a signal processing circuit whichhas a simple circuit configuration and is suitable for circuitintegration, specifically, a charge pump is often used in the past. Sucha charge pump is explained in detail for example in Behzad Razavi(author), Tadahiro Kuroda (translation supervisor), “A design andapplication of an analog CMOS integration circuit”, Maruzen CO., LMD.,March 2003, pp. 686-688.

FIG. 4 is a circuit block diagram illustrating an example of a signalprocessing circuit using a charge pump. The signal processing circuit 4illustrated in FIG. 4 is comprised of two switches SW1, SW2 and acapacitor 241.

In the signal processing circuit 4, when an UP signal is inputted fromoutside and the switch SW1 is closed to be “on”, an electric chargeflows from a voltage source Vdd having a higher voltage than a ground tothe capacitor 241, thereby increasing an output voltage. Here, an “on”resistance of the switch SW1 is not zero and a timewise change of anelectric charge, i.e., a current is finite. Therefore, the outputvoltage is not raised instantaneously to the voltage of the voltagesource Vdd.

On the other hand, when a DOWN signal is inputted from outside, theswitch SW2 turns on and the electric charge stored in the capacitor 241flows to the ground, thereby reducing the output voltage.

In addition, when both switches are off (open), an amount of theelectric charge stored in the capacitor 241 does not change, therebymaintaining the output voltage.

In such a signal processing circuit 4, the output voltage changes inaccordance with an integration over a time period of the UP signal andthe DOWN signal being inputted.

In the transceiver according to the above-stated conventional art, whena change of the control signal is larger than the adjusting signal, thereactance value at the time of the adjusting signal of C2 is larger thanthe reactance at the time of the adjusting signal of B2. Therefore, amagnitude relation between the adjusting signal and the reactance valueis reversed, thereby jeopardizing a control to obtain the maximum value.

By the way, in order to shorten a time that is needed to maximize theamplitude of the electric field induced in the living body 121 from thebeginning of reactance control, the control signal has to changelargely. However, in the configuration shown in FIG. 1, the controlsignal cannot be changed largely, thereby prolonging a time that takesuntil the maximum value is obtained.

In addition, since data to be transmitted is transmitted after thereactance control is finished, if it takes a long time until the maximumvalue is obtained, a time to be set aside for transmitting data becomesshort, thereby reducing an effective transmitting speed of data.

The above-stated signal processing circuit 4 as an integrator is oftenused in a Phase Locked Loop (PLL) circuit, which is an electric circuitthat enables a frequency of the output signal to coincide with areference frequency of the input signal or the like. In the PLL circuit,no large current flows from the voltage source Vdd to the ground, sincethe UP signal and the DOWN signal are not inputted into the circuit atthe same time.

On the other hand, when the signal processing circuit 4 is applied to acircuit in which the UP signal and the DOWN signal are both inputted atthe same time, the two switches SW1 and SW2 are both on. As a result, alarge current can flow from the voltage source Vdd to the ground,thereby leading to a disadvantage of increased power consumption.

DISCLOSURE OF INVENTION

The present invention has been made in view of the above circumstances.The objective thereof is to provide a transceiver that is configuredinto a control circuit that makes it possible to shorten a time thattakes to obtain the maximum value while maintaining stability, andenables a stable data communication at high speed.

Another objective of the present invention is to provide a signalprocessing circuit (an integrator) that is able to avoid an increase inpower consumption and is suitable for circuit integration, therebyreducing power consumption of communications apparatuses or the like.

In order to achieve the above objective, a first aspect of the presentinvention provides a transceiver in which an electric field based ondata to be transmitted is induced in an electric field transmittablemedium so as to transmit data using the induced electric field and toreceive data by receiving an electric field that is induced in theelectric field transmittable medium based on data to be received. Thetransceiver is comprised of a transmitting means that outputs analternating signal having a predetermined frequency, modulates thesignal with data to be transmitted and transmits the modulated signalaccording to the data; a transmitting-and-receiving electrode thatinduces an electric field based on the data to be transmitted andreceives an electric field based on the data to be received; a resonancemeans that is connected in series with the transmitting means and thetransmitting-and-receiving electrode to induce a series resonance byadjusting reactance against parasitic capacitance produced between aground of the transmitting means, the electric field transmittablemedium, and the earth ground; an electric field detection means thatdetects the electric field based on the data to be received and convertsthe electric field to an electric signal; an adjusting signal generationmeans outputting an adjusting signal for use in adjusting a reactancevalue of the resonance means; a amplitude detection means that includesa differential amplifying means having a first electric charge storingmeans storing the electric signal detected at the time of the reactancevalue being large, a second electric charge storing means storing theelectric signal detected at the time of the reactance value being smallin adjusting the reactance of the resonance means, a detection meansdetecting an electric field amplitude at the time of the reactance beinglarge, and a filter eliminating a high-frequency component from thedetected electric field and amplifies the difference between theelectric field amplitudes at the time of the reactance value being largeand at the time of the reactance value being small in adjusting thereactance of the resonance means in order to detect an amplitude of theelectric signal outputted from the electric field detection means usingthe adjusting signal outputted from the adjusting signal generationmeans, and a constant voltage source generating a constant voltagesignal; a control signal generation means generating a control signal tocontrol a characteristics of the resonance means based on the amplitudedetected by the amplitude detection means; and a demodulation meansdemodulating the electric signal converted by the electric fielddetection means.

A second aspect of the present invention provides a transceiveraccording to the first aspect, wherein the control signal generationmeans includes an integrator integrating an output signal from thedifferential amplifying means to produce the integrated signal and anadder adding the signal produced by the integrator and the adjustingsignal outputted from the adjusting signal generation means.

A third aspect of the present invention provides a transceiver accordingto the second aspect, wherein the integrator includes a voltagecomparator comparing the electric field amplitudes at the time of thereactance value being large and small, a first p-channel MOS-FET and asecond n-channel MOS-FET that are off at the time of detecting theamplitude and on at the time of integrating, a second p-channel MOS-FETand a first n-channel MOS-FET that turn on the second p-channel MOS-FETand turn off the first n-channel MOS-FET so as to increase an outputvoltage when the electric field amplitude at the time of the reactancevalue being large is larger and turn off the second p-channel MOS-FETand turn on the first n-channel MOS-FET so as to reduce the outputvoltage when the electric field amplitude at the time of the reactancevalue being large is small, and a capacitor maintaining the controlsignal.

A fourth aspect of the present invention provides a transceiveraccording to the third aspect, wherein the integrator in the thirdaspect includes a first constant voltage source outputting apredetermined first threshold, a second constant voltage sourceoutputting a predetermined second threshold, a first voltage comparatoroutputting a result obtained by comparing the first threshold and anoutput of the differential amplifying means, and a second voltagecomparator outputting a result obtained by comparing the secondthreshold and an output of the differential amplifying means.

A fifth aspect of the present invention provides a transceiver accordingto the fourth aspect, wherein the integrator in the fourth aspectincludes a first variable resistor controlling a change rate of avoltage of the control signal when the voltage is increased, a secondvariable resistor controlling a change rate of a voltage of the controlsignal when the voltage is decreased, a first differential amplifierthat compares the first threshold and an output of the differentialamplifying means and thus outputs a signal controlling the firstvariable resistor and a second differential amplifier that compares thesecond threshold and an output of the differential amplifying means andthus outputs a signal controlling the second variable resistor.

A sixth aspect of the present invention provides a transceiver accordingto the fourth aspect, wherein there is provided a sampling meanssampling the electric signal outputted from the electric field detectionmeans, instead of the detection means and the filter.

A seventh aspect of the present invention provides a transceiveraccording to the fourth aspect, wherein there is provided a peak-holdmeans maintaining a peak of the amplitude of the electric signaloutputted from the electric field detection means, instead of thedetection means and the filter.

In an eighth aspect of the present invention, the peak-hold meansaccording to the seventh aspect has an adding means that detects thepeak for a predetermined number of times to add and maintains the addedvalue.

In order to achieve the above objective, a ninth aspect of the presentinvention provides a signal processing circuit. The signal processingcircuit is comprised of an electric charge storing means storing anelectric charge so as to maintain an output voltage, a first connectionmeans being closed when an electric charge is stored in the electriccharge storing means so as to increase the output voltage, a secondconnection means being closed when the electric charge stored in theelectric charge storing means is transferred to the ground so as todecrease the output voltage, a first signal comparison means thatcompares a signal inputted from outside and a predetermined firstthreshold and outputs a control signal to close the first connectionmeans when the inputted signal is lower, and a second signal comparingmeans that compares the inputted voltage and a second threshold that ispredetermined to have a higher voltage value than the first thresholdand outputs a control signal to close the second connection means whenthe inputted voltage is lower.

A tenth aspect of the present invention provides a signal processingcircuit according to the ninth aspect, in which there is provided afirst and a second current source that are connected in series with thefirst and the second connection means, respectively, to produce acurrent, a third signal comparison means that compares the inputtedvoltage and a third threshold that is predetermined to have a lowervoltage than the first threshold and outputs a current control signal tothe first current source to cause the first current source to flow afirst constant current having a predetermined value when the inputtedvoltage is lower than the third threshold and outputs a current controlsignal to the first current source to cause the first current source toflow a second constant current having a smaller current value than thefirst constant current, a fourth signal comparison means that comparesthe inputted voltage and a fourth threshold that is predetermined tohave a larger voltage than the second threshold and outputs a controlsignal to the second current source to cause the second current sourceto flow a constant current having the same current value as the firstconstant current when the inputted voltage is higher than the fourththreshold and outputs a current control signal to the second currentsource to cause the second current source to flow a constant currenthaving the same current value as the second constant current when theinputted voltage is higher than the second threshold and lower than thefourth threshold.

An eleventh aspect of the present invention provides a signal processingcircuit according to the ninth aspect, wherein a first and a secondcurrent source connected in series with the first and the secondconnection means, respectively, to produce a current, a firstdifferential amplifying means that obtains a difference between theinputted voltage and the first threshold and outputs acontinuously-changeable current control signal to the first currentsource so that the lower the inputted voltage is the larger the currentflows from the first current source, and a second differentialamplifying means that obtains a difference between the inputted voltageand the second threshold and outputs a continuously-changeable currentcontrol signal to the second current source so that the larger theinputted voltage is the larger the current flows from the second currentsource.

According to the present invention, there is provided a transceiver thatis configured into a control circuit that makes it possible to shorten atime that takes to obtain the maximum value while maintaining stability,and enables a stable data communication at high speed.

In addition, according to the present invention, there is provided asignal processing circuit suitable in integration, in which a largecurrent is prevented from flowing when an observed value and a targetvalue are met, thereby preventing an increase in power consumption.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram of a conventional transceiver;

FIG. 2A is an explanatory drawing of an operation of the conventionaltransceiver;

FIG. 2B is an explanatory drawing of an operation of the conventionaltransceiver;

FIG. 3A is an explanatory drawing of an operation of the conventionaltransceiver;

FIG. 3B is an explanatory drawing of an operation of the conventionaltransceiver;

FIG. 4 is a circuit block diagram illustrating a configuration of aconventional signal processing circuit;

FIG. 5 is an overall block diagram of a transceiver according to a firstembodiment of the present invention;

FIG. 6A illustrates a waveform outputted from each component or elementof the transceiver according to the first embodiment of the presentinvention;

FIG. 6B is an explanatory drawing of an operation of the transceiveraccording to the first embodiment of the present invention;

FIG. 7 is a block diagram illustrating a configuration of a signalprocessing circuit preferable as an integrator of the transceiveraccording to the first embodiment of the present invention;

FIG. 8 illustrates a relation between an output voltage (OUT1, OUT2) ofan electric signal comparator and an input voltage (IN) in the signalprocessing circuit in FIG. 7;

FIG. 9 is a circuit block diagram illustrating a configuration of asignal processing circuit preferable as an integrator of the transceiveraccording to the first embodiment of the present invention;

FIG. 10 illustrates relations between an output signal (OUT1, OUT2) ofan electric signal comparator and an input voltage (IN) and between acurrent (I1, I2) flown from a current source and an input voltage in thesignal processing circuit in FIG. 9;

FIG. 11 is a circuit block diagram illustrating a configuration of asignal processing circuit preferable as an integrator of the transceiveraccording to the first embodiment of the present invention;

FIG. 12 illustrates a relation between a current control signal and acurrent flown from a variable current source;

FIG. 13 illustrates relations between an output signal (OUT1, OUT2) ofan electric signal comparator and an input signal (IN) and between acurrent (I1, I2) flown from a current source and an input signal in thesignal processing circuit in FIG. 11;

FIG. 14 is an overall block diagram of a transceiver according to asecond embodiment of the present invention;

FIG. 15 is an overall block diagram of a transceiver according to athird embodiment of the present invention;

FIG. 16 is an explanatory drawing of an operation of the transceiveraccording to the third embodiment of the present invention;

FIG. 17 is a schematic diagram of a control section of a transceiveraccording to a fourth embodiment of the present invention;

FIG. 18 is a schematic diagram of a control section preferable to atransceiver according to a fifth embodiment of the present invention;

FIG. 19 is an overall schematic diagram of a configuration of atransceiver according to a sixth embodiment of the present invention;

FIG. 20 is an explanatory drawing of an operation of the transceiveraccording to the sixth embodiment of the present invention;

FIG. 21 is an overall schematic diagram of a transceiver according to aseventh embodiment of the present invention;

FIG. 22 is an explanatory drawing of an operation of the transceiveraccording to the seventh embodiment of the present invention;

FIG. 23 is an explanatory drawing of an operation of the transceiveraccording to the seventh embodiment of the present invention;

FIG. 24 is an overall schematic diagram of a transceiver according to aneighth embodiment of the present invention;

FIG. 25 is a partial schematic diagram of the transceiver according tothe eighth embodiment of the present invention;

FIG. 26 is an explanatory drawing of an operation of the transceiveraccording to the eighth embodiment of the present invention;

FIG. 27 is an overall schematic diagram of a transceiver according to aninth embodiment;

FIG. 28 is an overall schematic diagram of a transceiver according to atenth embodiment; and

FIG. 29 is a block diagram illustrating an amplifier circuit to whichthe signal processing circuits can be applied.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to accompanying drawings, a transceiver according to preferredembodiments of the present invention will be described hereinafter. Thetransceiver described hereinafter includes a reactance adjusteraccording to an embodiment of the present invention. Thus, the reactanceadjuster also will be described below.

A First Embodiment

FIG. 5 is a block diagram of a transceiver according to a firstembodiment of the present invention. The transceiver according to thefirst embodiment illustrated in FIG. 5 is comprised of an oscillator 5outputting an alternating electric signal to be a carrier having afrequency of about 1 megahertz (MHz) to several tens MHz, a modulationcircuit 6 modulating the carrier wave using data to be transmittedobtained from a computer (not shown) via an Input/Output circuitdescribed hereinafter, a switch 2 turning on at the time of adjustingreactance or transmitting and turning off at the time of receiving, avariable reactance section 7 inducing resonance with parasiticcapacitance between a living body and an earth or between a groundcontact of the transceiver and the earth, a switch 3 connecting acontact a3 with a contact b3 so as to charge a capacitor C1 with thedetected signal when a large reactance is detected and connecting thecontact a3 with the contact c3 to charge a capacitor C2 with thedetected signal when a lower reactance value is detected duringreactance adjustment, a detector 8 and a filter 9 detecting an electricamplitude when the reactance value is large, a differential amplifier 10obtaining a difference of the electric amplitudes between when thereactance value is large and when the reactance value is small, anintegrator 11 integrating an output signal and outputting a controlsignal for controlling the reactance, a switch 4 connecting a contact a4with a contact c4 to input a signal from a constant voltage source 12 soas to keep the output of the integrator unchanged when detecting theelectric amplitude and connecting the contact a4 with the contact c4 soas to input the signal from the differential amplifier 10 whenintegrating, the constant voltage source 12 outputting an electricsignal having a zero value to the integrator 11, an adjusting signalsource 13 outputting an adjusting signal for use in adjusting areactance value, an adder 14 adding the adjusting signal and thecontrolling signal to output the added signal to the variable reactancesection 7, an electric field detecting optical section 15 converting anelectric field produced in a living body 121 to an electric signal, asignal processing section 16 amplifying the outputted signal from theelectric field detecting optical section 15 and eliminating noise usinga filter (not shown), a demodulation circuit 17 demodulating a receivedsignal, a waveform shaping section 18 shaping a waveform, and a switch 1connecting a contact al with a contact b1 so as to input the outputtedsignal from the signal processing portion at the time of reactanceadjusting and transmitting and connecting the contact al with a contactcl so as to input the signal to the demodulator 17 at the time ofreceiving.

Referring to FIGS. 5, 6A and 6B, an operation of the reactance adjusterin the transceiver according to the first embodiment will be describedfirst. A predetermined signal outputted by the oscillator 5 and themodulation circuit 6 is supplied to a transmitting-and-receivingelectrode 123 via the switch 2 and the variable reactance section 7 andthe electrode 123 induces an electric field based on the signal in theliving body 121. The predetermined signal mentioned here can bearbitrarily selected as far as the signal is suitable for adjusting areactance value. For example, the predetermined signal may be a carrieroutputted from the oscillator 5 or a modulated signal obtained bymodulating the carrier according to data to be transmitted. In addition,there can be provided a signal generation section that is separated fromthe oscillator 5 and modulation circuit 6.

The electric field is received by the electric field detecting opticalsection via the transmitting-and-receiving electrode 123 and transformedinto an electric signal. This electric signal is treated by the signalprocessing section 16 so that noise is eliminated therefrom and then ledto the switch 3 via the detector 8 and the filter 9 by connectionbetween the contacts a1 and b1 in the switch 1. The detector 8 hasfunctions of transforming the electric signal from the signal processingsection 16 into a direct voltage according to an amplitude of the signaland eliminating a higher harmonics component from an electric voltageoutputted from the detector 8.

On the other hand, whilst the predetermined signal concerned is suppliedto the transmitting-and-receiving electrode 123, a high level signal (H)and a low level signal (L) as an adjusting signal A are alternativelyapplied to the variable reactance section 7 via the adder 14 (FIG. 6A).An application of the adjusting signal A causes a reactance of thevariable reactance section 7 to change. In the following description,unless otherwise noted, when the high level signal from the adjustingsignal source 13 is applied to the variable reactance section 7, thereactance of the variable reactance section 7 becomes higher, and whenthe low level signal from the adjusting signal source 13 is applied tothe variable reactance section 7, the reactance becomes lower.

An adjusting signal B for controlling a switching of the switch 3 isoutputted from the adjusting signal source 13 in synchronization withthe adjusting signal A. Specifically, when the adjusting signal source13 outputs a high level signal to the variable reactance section 7, thecontacts a3 and b3 are connected in the switch 3. This connection allowsthe capacitor C1 to be charged by the direct voltage obtained by thedetector 8 converting the electric signal, when the adjusting signalsource 13 outputs a high level signal. On the other hand, when theadjusting signal source 13 outputs a low level signal, the capacitor C2is charged by the direct voltage based on the electric signal.

While either one of the capacitors C1 and C2 is charged, the contacts b4and c4 are connected in the switch 4 by an adjusting signal C from theadjusting signal source 13. Therefore, the zero voltage from theconstant voltage source 12 is inputted into the integrator 11 and theoutput of the integrator 11 is not varied. When the charging of thecapacitors C1 and C2 ends, the contacts a4 and b4 in the switch 4 areconnected according to the adjusting signal C. Therefore, a voltage(voltage having a predetermined voltage value) based on the differencebetween the voltages across the capacitors C1 and C2 is inputted to theintegrator 11 from the differential amplifier 10.

In the transceiver according to the first embodiment of the presentinvention, as shown in FIGS. 6A and 6B, in order to keep the output ofthe integrator 11 unchanged while detecting an electric field amplitudeby providing the switch 4 between the differential amplifier 10 and theintegrator 11, an operation cycle of “a detection of an electric fieldamplitude when a reactance is high”, “a detection of an electric fieldamplitude when a reactance is low”, and “an integrating of thedifference between the two amplitudes” is realized. When the reactanceis high, the contacts a3 and c3 are connected, thereby charging thecapacitor C2 with the signal of which field amplitude is detected by thedetector 8 and the filter 9. When the reactance is low, the contacts a3and c3 are connected, thereby charging the capacitor C2 with theamplitude-detected signal. During these periods, the contact a4 isconnected to the contact c4 connected to the constant voltage source 12for transmitting a signal having zero value to the integrator 11 in theswitch 4, thereby keeping the output of the integrator 11 unchanged.After the detection of the amplitude, the contact a3 is connected toneither the contact b3 nor the contact c3 in the switch 3, whereas thecontact a4 and the contact b4 are connected to performing integration.By the way, NCs representing one connection state of the switch 3 inFIG. 6A show that the contact a3 is connected to neither the contact b1nor the contact c1.

According to the above operation, since the output (control signal) ofthe integrator 11 is unchanged during the detection of an electric fieldamplitude, even when a change of the control signal is larger than theamplitude of the adjusting signal A, a relation between a swing of thereactance value and the adjusting signal A is not inversed so that anormal operation is feasible. As a result, time required to determinethe maximum value is shortened, thereby realizing a stable and effectivedata transmission at high speed.

While FIG. 6A illustrates where the adjusting signal A is set as a lowlevel during integration during the adjusting signal C being a highlevel, the normal operation is realized even when the signal A can beset as a high level. In addition, there can be used a signal from anoscillating device as a signal source that generates the adjustingsignals A, B, and C. Moreover, while the capacitors C1 and C2 are usedin order to store an electric signal representative of the electricfield amplitude, another storing means is feasible in order to realizethe same operation. For example, a memory device can be used as thestoring means.

Under the circumstances in which the reactance is appropriatelycontrolled, a signal to be transmitted is outputted to the modulationcircuit 6 via an I/O circuit 122 and thus a modulated signal is obtainedby modulating the carrier supplied from the oscillator 5 based upon thesignal to be transmitted, thereby inducing an electric field accordingto the modulated signal inside the living body 121.

Moreover, the contacts al and cl are connected in the switch 1, therebyproviding an electric signal from the electric field detecting opticalsection 15 to the demodulation circuit 17. A signal to be received,which is contained in the electric signal, is demodulated by thedemodulation circuit 17, wave-formed by the waveform shaping section 18,and then supplied to a computer via the I/O circuit 122, the computermanaging a signal to be transmitted or received. In this manner, aninformation communication is realized between a transceiver and anotherwith the living body 121 interposed therebetween.

By the way, when another modulation method, for example, phasemodulation or frequency modulation, in which the amplitude of thecarrier is kept constant, is adopted, the amplitude value is allowed tochange since the amplitude does not have any information. Therefore, inthis case, the output of the adjusting signal source needs not to beterminated during a transmission of data.

As modifications of the transceiver according to the first embodiment,the integrator 11 having the following configuration will be describedhereinafter.

(A First Modification)

FIG. 7 is a circuit block diagram illustrating a signal processingcircuit suitable as an integrator of the transceiver according to thefirst embodiment. In a signal processing circuit 100, a voltage V1having a slightly lower voltage value than a target voltage value and avoltage V2 having a slightly higher voltage value than the targetvoltage value are used as threshold voltages. The signal processingcircuit 100 is designed so that both switches SW1 and SW2 are inpositive logic in the signal processing circuit 100, an electricalsignal comparator 11 exhibits a higher voltage when an input voltage islower than V1 and an electric signal comparator 12 exhibits a highervoltage when an input voltage is higher than V2.

Specifically, the signal processing circuit 100 has the followingconfiguration. Namely, the signal processing circuit 100 is comprised ofan electric signal comparator 211 that compares an input voltage INinputted from outside with the threshold V1 and outputs a signal OUT1 toturn on the switch SW1 as a first connection means when the inputvoltage IN is lower than the threshold voltage V1, an electric signalcomparator 212 that compares the input voltage IN with the threshold V2and outputs a signal OUT2 to turn on the switch SW2 as a secondconnection means when the input voltage IN is higher than the thresholdvoltage V2, and a capacitor 213 storing an electric charge so as tomaintain an output voltage.

The input voltage IN is a voltage having a predetermined voltagesupplied from the constant voltage source 12 via the switch 4 (FIG. 5)in the transceiver according to the first embodiment or a voltage fromthe differential amplifier 10. The voltage across the capacitor 213 isapplied to the variable reactance section 7 (FIG. 5) of the transceiver.

FIG. 8 illustrates a relation between an output voltage OUT1 or OUT2(vertical axis) outputted from an electric signal comparator and aninput voltage IN (horizontal axis) in the signal processing circuit.

According to a line 2101 shown in FIG. 8, when the input voltage IN hasa voltage value between a range of the threshold voltage V1 and thethreshold voltage V2, the range including a target voltage value, theelectric signal comparators 211 and 212 do not output the signal OUT1and OUT2, thereby turning off the switches SW1 and SW2 (open).Therefore, the output voltage remains unchanged and thus a large currentdoes not flow.

On the other hand, when the input voltage IN is lower than the thresholdV1, the signal OUT1 is outputted to turn on the switch SW1 and theswitch SW2 is kept off. Therefore, an electric charge is transferredfrom a voltage source Vdd to the capacitor 213 through the switch 1,thereby increasing a voltage across the capacitor 213 so as to be equalto the voltage of the voltage source Vdd.

In addition, when the input voltage IN is higher than the thresholdvoltage V2, the signal OUT2 is outputted to turn on the switch 2 and theswitch SW1 is kept off. In this case, the electric charge stored in thecapacitor 213 is transferred to the earth ground through the switch 2,thereby decreasing a voltage across the capacitor 213.

By the way, in the transceiver that uses the signal processing circuit100 as the integrator, while either the electric charge storing means C1or C2 (FIG. 5) is storing electric charge, the contacts a4 and b4 areconnected in the switch 4, thereby providing the voltage of the constantvoltage source 12 to the signal processing circuit 100. This voltage hasa voltage value between the thresholds V1 and V2. Therefore, when theelectric charge means C1 and C2 are storing electric charge, neither theswitch SW1 nor the switch SW2 is on, thereby maintaining the outputvoltage (the control signal) of the signal processing circuit 100 at avoltage across the terminals of the capacitor 213.

According to the signal processing circuit 100 described above as theintegrator 11, neither the switch SW1 nor the switch SW2 is turned on,no large current flows from the voltage source Vdd to the earth ground,thereby preventing a power consumption from increasing. Therefore, thereis provided a signal processing circuit suitable for circuitintegration.

(A Second Modification)

FIG. 9 is a circuit block diagram illustrating a configuration ofanother signal processing circuit preferable as an integrator for use inthe transceiver according to the first embodiment of the presentinvention. Referring to FIG. 9, a signal processing circuit 200 ischaracterized in that, there is a current source 225 between thepositive electrode of a power source Vdd and the switch SW1, there is acurrent source 226 between the earth ground and the switch SW2, andthereby electric signal comparators 223 and 224 output a current controlsignal to the current sources 225 and 226, respectively, to adjust acontrol signal. In addition, in the signal processing circuit 200, theswitches SW1 and SW2 are in positive logic.

By the way, the signal processing circuit 200 is substantially the sameas the signal processing circuit 100 described above in that the signalprocessing circuit 200 is comprised of an electric signal comparator 221that compares an input voltage IN inputted from outside with thethreshold V1 and outputs the signal OUT1 to turn on the switch SW1 as afirst connection means when the input voltage IN is lower than thethreshold voltage V1, an electric signal comparator 222 that comparesthe input voltage IN with the threshold V2 and outputs an signal OUT2 toturn on the switch SW2 as a second connection means when the inputvoltage IN is higher than the threshold voltage V2, and a capacitor 227storing an electric charge so as to maintain an output voltage.

In addition, the input voltage IN is a voltage having a predeterminedvoltage value, which is supplied from the constant voltage source 12 viathe switch 4 (FIG. 5), or a voltage supplied from the differentialamplifier 10 via the switch 4. Moreover, a voltage across the terminalsof the capacitor 213 is applied to the variable reactance section 7(FIG. 5) of the transceiver, as is the case with the signal processingcircuit 100.

In addition to the above features, the signal processing circuit 200 isfurther comprised of an electric signal comparator 223 that compares theinput voltage IN with a third threshold value V3 (<V1) and outputs acurrent control signal to cause the current source 225 to flow a largecurrent when the input voltage NI is lower than the third thresholdvalue V3, and an electric signal comparator 224 that compares the inputvoltage with a fourth threshold voltage V4 (>V2) and outputs a currentcontrol signal to cause the current source 226 to flow a large currentwhen the input voltage IN is higher than the fourth threshold voltageV4.

An operation of the signal processing circuit 200 having the aboveconfiguration will be described hereinafter. The two current sources 225and 226 that are connected in series with the switches SW1 and SW2,respectively, output a current having a different current value,depending on the current control signal of 1 or 0 outputted from theelectric signal comparators 223 and 224 that are connected to thecurrent sources 225 and 226, respectively.

FIG. 10 illustrates a relation between a current I1 flowing through theswitch 1 and a current I2 flowing through the switch 2, in which apositive direction of each current is in accordance with an arrow shownin FIG. 9.

According to a ling 2201 in FIG. 10, when the input voltage is lowerthan V3, the current control signal having a value of 1 is outputtedfrom the electric signal comparator 223 to the current source 225. Inresponse to this, the current I1 (a first constant current) flows fromthe current source 225 as shown by the line 2201 in FIG. 10. As aresult, an output voltage (across a capacitor 227) is increased.

When the input voltage is higher than V3 and lower than V1, the currentcontrol signal having a value of 0 is outputted from the electric signalcomparator 223 to the current source 225 and thus a current (a secondconstant current) having a lower current value than the current Ii flowsfrom the current source 225. As a result, the output voltage increasesgradually, compared with the case where the current I1 flows from thecurrent source 225.

As shown in FIG. 10, a current having a high or a low current valueflows from the current source 225 depending whether the current controlsignal value outputted from the electric signal comparator 223 is 1 or0. Namely, when the input voltage deviates largely from the targetvalue, the current having a large current value flows from the currentsource 225 and then the output voltage (the capacitor 227) increasesswiftly, and when the input voltage deviates slightly from the targetvalue, the current having a low current value flows from the currentsource 225 and then the output voltage increases gradually.

On the other hand, when the input voltage is higher than V4, theelectric signal comparator 224 outputs the current control signal of 1and thus the current source 226 flows a large current I2 (a thirdconstant current). As a result, the output signal decreases swiftly. Bythe way, the current value of the current I2 can be the same as that ofthe current I1 (the first constant current).

When the input voltage is higher than V2 and lower than V4, the electricsignal comparator 224 outputs a current control signal having a value of0 to the current source 226 and then the current source 226 flows acurrent (a fourth constant current) having a lower current value thanthe current I2. Therefore, the electric charge stored in the capacitor227 discharges to the earth ground more slowly compared with the casewhere the current I2 flows from the current source 226, therebydecreasing gradually the output voltage. By the way, the fourth constantcurrent can have the same current value as the second constant current.

The current source 226 outputs a current having a large or a smallcurrent value depending whether the current control signal outputtedfrom the electric signal comparator 224 is 1 or 0, as is the case withthe current source 225.

By using the current sources 225 and 226 having such a function, when adeviation between the input voltage and the target value is large, acurrent having a large current value flows, thereby changing the outputvoltage swiftly, and when the deviation is small, a current having a lowcurrent flows, thereby changing the output voltage slowly. Therefore,the circuit operates with a higher stability.

In summary, according to the signal processing circuit 200 describedabove as the integrator 11, the same effect as the above signalprocessing circuit 100 is obtained.

In addition, according to the signal processing circuit 200, since thecurrent sources are connected in series with the switches, the outputvoltage can be changed depending on the deviation between the inputvoltage and the target value, thereby further improving a stability ofthe signal processing circuit.

(A Third Modification)

FIG. 11 is a circuit block diagram illustrating yet another signalprocessing circuit suitable as the integrator 11 of the transceiveraccording to the first embodiment of the present invention. As shown inFIG. 11, in a signal processing circuit 203, there is connected avariable current source 235 between the switch SW1 and the positiveelectrode of the voltage source Vdd and there is connected a variablecurrent source 236 between the switch SW2 and the earth ground, whereinan electric control signal is inputted to the variable current sources235 and 236 from the differential amplifiers 233 and 234, respectively.The differential amplifier 233 inputs the threshold V1 (a positive phaseinput) and the input voltage IN (a negative phase input) and outputs acurrent control signal to the variable current source 235 so that thelarger the difference between the threshold V1 and the input voltage INis, the larger the current flows from the variable current source 235.The differential amplifier 234 inputs the input voltage IN (a positivephase input) and the threshold V2 (a negative phase input) and outputs acurrent control signal to the variable current source 236 so that thelarger the difference between the input voltage IN and the threshold V2is, the larger the current flows from the variable current source 236.

By the way, also in the signal processing circuit 203, the switches SW1and SW2 are both in positive phase.

In addition, the signal processing circuit 203 is composed of anelectric signal comparator 231 that compares the first threshold V1 andthe input voltage IN and outputs a signal OUT1 to turn on the switch SW1when the input voltage IN is lower than the threshold V1, an electricsignal comparator 232 that compares the second threshold V2 and theinput voltage IN and outputs a signal OUT2 to turn on the switch SW2when the input voltage IN is higher than the threshold V2, and acapacitor 237 that stores electric charge so as to maintain the outputvoltage at constant as is the case with the above signal processingcircuits 100 and 200.

In the signal processing circuit 203, since the current control signaloutputted to the variable current sources 235 and 236 respectively fromthe differential amplifiers 233 and 234 change continuously, as arelation between the current control signal and the current outputtedfrom the variable current source is shown by a characteristic line 301in FIG. 12, a current value of the current from the current sourcechanges continuously in accordance with the current control signal.

FIG. 13 illustrates a relation between the input voltage IN and thecurrents Ii and I2 outputted from a variable current source when thevariable current source that has a characteristic line 2301 shown inFIG. 12. As stated above, the input voltage IN is inputted to the twodifferential amplifiers 233 and 234 in an opposite phase with eachother. Specifically, the input voltage IN is inputted, on one hand, tothe inverting terminal (−) of the differential amplifier 233 and, on theother hand, to the non-inverting terminal (+) of the differentialamplifier 235. As a result, a line 2401 that is symmetrical to an axispassing through the target value is obtained as shown in FIG. 7. Nothingto say that the absolute slop of the line 2401 representing the currentvalues I1 and I2 is the same as the absolute slope of the line shown inFIG. 12.

When the input voltage IN is lower than the threshold V1, thedifferential amplifier 233 outputs a current control signal to thevariable current source 235 in a manner that the lower the input voltageIN is than the threshold V1, the larger the current from the variablecurrent source 235 becomes. Therefore, the larger the current flows fromthe current source 235, thereby increasing swiftly the output voltage.In addition, in the signal processing circuit 203, the higher the inputvoltage IN is, the smaller the current I1 becomes, thereby increasingthe output slowly.

On the other hand, when the input voltage IN is higher than thethreshold V2, the current source 236 flows the current I2, therebyreducing the output voltage. Namely, the higher the input voltage IN is,the more swiftly the output voltage is reduced.

When the input voltage IN is higher than the threshold V1 and lower thanthe threshold V2, no current flows, thereby maintaining the outputvoltage constant.

According to the signal processing circuit 203 described above as theintegrator ii, the same effect as the above-stated signal processingcircuit 100 is obtained.

In addition, according to the signal processing circuit 203, byconnecting the variable current source in series with the switch, theoutput voltage can be changed depending on a deviation between the inputvoltage and the target value, thereby further improving a stability ofthe signal processing circuit.

(A Fourth Modification)

Instead of the current sources 235 and 236 provided in the thirdmodification, a variable resistor can be provided. In this case, theelectric signal comparators 233 and 234 are configured to output acurrent control signal to the variable resistor in a manner that thelarger the difference between a predetermined voltage (IN) and constantvoltages V1 or V2 is, the lower the resistance of the variable resistorbecomes. With this, the larger the deviation between the predeterminedvoltage and the constant voltage is, the larger the current flows,thereby increasing the output voltage swiftly. When a difference betweenthe predetermined voltage and the constant voltage is small, theresistance of the variable resistor becomes large, thereby changing thecurrent value slowly. Therefore, the reactance adjusting is accomplishedstably in a short time.

A Second Embodiment

Next, a transceiver according to a second embodiment of the presentinvention will be described hereinafter. In the second embodiment, aspecific configuration of an integrator is described. FIG. 14illustrates a transceiver according to the second embodiment, in which acharge pump circuit is used as the integrator.

As shown in FIG. 14, an integrator 20 is composed of a pMOS1, a pMOS2,an nMOS1, and an nMOS2 that are connected in this order between thepositive electrode of a voltage source for the integrator and the earthground in series with one another, and a capacitor Cp that is connectedbetween a node between the pMOS2 and the nMOS1 and the earth ground inseries with the nMOS1 and the nMOS2. Here, pMOS indicates a p-channelMOS-FET (Metal Oxide Semiconductor Field Effect Transistor) and nMOSindicates an n-channel MOS-FET.

When the capacitors C1 and C2 are storing electric charge, the pMOS1 andthe nMOS2 is off so as to prevent an output voltage (a voltage across acapacitor Cp) of the integrator 20 from changing. When the capacitors C1and C2 stop storing electric charge, the pMOS1 and the nMOS2 is turnedon.

By the way, as shown in FIG. 14, an adjusting signal C is inputted tothe gate of pMOS1 from an adjusting signal source 13 via a voltagereversing device. To the gate of the nMOS2 is directly inputted theadjusting signal C from the adjusting current source 13. The adjustingsignal C is a signal produced based on the adjusting signal B forcontrolling an electric charge storing by the capacitors C1 and C2.Namely, the adjusting signal source 13 outputs a low level signal as theadjusting signal C while the capacitors C1 and C2 are storing anelectric charge and outputs a high level signal when the capacitor C1and C2 terminates the electric charge stroing (FIG. 16). Therefore, thepMOS1 and the nMOS2 are controlled so as to be off while the capacitorsC1 and C2 are storing electric charge and on when the electric chargestoring ends.

On the other hand, to the gate of the pMOS2 and the nMOS1 is inputted asignal from a voltage comparator 10. The voltage comparator 10 comparesa voltage across the capacitor C1 and a voltage across the capacitor C2and outputs a low level signal when the voltage across the capacitor C1is higher than that across the capacitor C2. Because of this, the pMOS2is on and the nMOS1 is off. When the capacitors C1 and C2 stop storingan electric charge and the pMOS1 (and the nMOS2) is on by the adjustingsignal C, an electric charge is transferred to the capacitor Cp via thepMOS1 and the pMOS2 from the voltage source, thereby increasing thecontrol signal voltage.

The other way around, when the voltage across the capacitor C1 is lowerthan that across the capacitor C2, the voltage comparator 10 outputs ahigh level signal. Therefore, the pMOS2 is off and the nMOS1 is on. Whenthe capacitors C1 and C2 stop storing an electric charge and the nMOS2(and the pMOS1) is on by the adjusting signal C, an electric charge istransferred to the earth ground via the nMOS1 and the nMOS2, therebyreducing the control signal voltage.

When comparing the second embodiment with the first modification of thefirst embodiment, the pMOS2 has the same function as the switch SW1; thenMOS1 has the same function as the switch SW2; and the pMOS1 and thenMOS2 have the corresponding function as the switch 4. The pMOS1 and thenMOS2 are off when the adjusting signal C is at a low level and thus noelectric charge is transferred. As a result, the output voltage (controlsignal) is maintained at the voltage across the capacitor Cp. In otherwords, in the transceiver according to this embodiment, the controlsignal is prevented from being fluctuated when the capacitors C1 and C2are storing an electric charge without using the constant voltage source12 in the first embodiment.

With the above configuration, the transceiver according to thisembodiment exhibits the same effect as the transceiver according to thefirst embodiment.

FIG. 15 illustrates a block diagram of a transceiver according to athird embodiment.

Referring to FIG. 15, the transceiver according to the third embodimentis comprised of a pMOS1 and an nMOS2 that are off so as not to changethe output of an integrator during an amplitude detection and are onduring an integration, a capacitor Cp for maintaining the output voltage(control signal), a constant voltage source SX outputting a threshold X(reference voltage), a constant voltage source SY outputting a thresholdY (reference voltage), a voltage comparator X outputting a voltageresulted by comparing the threshold X and the output of the differentialdetector 22, and a voltage comparator Y outputting a voltage resulted bycomparing the input signal and the threshold Y.

The transceiver according to the third embodiment is provided with avoltage comparator X and a voltage comparator Y each having a thresholdX and a threshold Y in a front stage of a charge pump circuit. Thedifferential detector 22 performs a voltage level conversion so as tooutput a constant voltage when there is no difference between inputsignals. A constant voltage source SX and a constant voltage source SYshown in FIG. 15 are a signal source for providing respectively thevoltage comparator X and the voltage comparator Y with a threshold. FIG.16 illustrates a waveform of an output of each component duringcontrolling. As shown in FIG. 16, the threshold X and the threshold Yare set so as to have a convergence value therebetween. Here, theconvergence value of the differential detector 22 indicates an electricsignal outputted when there is no difference between the input signals.

In a control section 21, when the voltage across the capacitor C1 ishigher than that across the capacitor C2 and the output of thedifferential detector 22 is higher than the thresholds X and Y, sincethe voltage comparators X and Y output a low level signal, the pMOS2 ison and the nMOS1 is off. When the voltage across the capacitor C1 issubstantially the same as that across the capacitor C2 and the output ofthe differential detector 22 lies between the threshold X and thethreshold Y, since the output of the voltage comparator X is at a highlevel and the output of the voltage comparator Y is at a low level, boththe pMOS2 and the nMOS1 are off. When the voltage across the capacitorC1 is lower than that across the capacitor C2 and the output of thedifferential detector 22 is lower than the threshold X and threshold Y,since the outputs of the voltage comparators X and Y are both at a highlevel, the pMOS2 is off and the nMOS1 is on.

Therefore, when the electric field amplitude at the time of a highreactance value is larger than the electric field amplitude at the timeof a low reactance value, i.e., when the voltage across the capacitor C1is higher than that across the capacitor C2, the control signal becomeslarge, and when smaller, the control signal becomes small. Therefore,the same operation as the control circuit according to the firstembodiment is realized.

However, whereas the control signal continues to change until theelectric field amplitude at the time of a large reactance value iscompletely the same as the electric field amplitude at the time of asmall amplitude in the first embodiment, a difference between the twoamplitudes is permissible in the third embodiment. Because of this, thecontrol signal is not changed by an error in the electric fieldamplitude due to a noise caused in an electrical circuit or the likeused in the transceiver (a differential detection output in FIG. 16).Therefore, compared with the transceiver according to the firstembodiment, the transceiver according to the third embodiment has ahigher stability in terms of noise.

A Fourth Embodiment

FIG. 17 is a schematic diagram of a control section 23 suitable for atransceiver according to a fourth embodiment. Referring to FIG. 17, thecontrol section 23 has a pMOS1, a pMOS2, an nMOS1, an nMOS2, a capacitorCp, a constant voltage source SX outputting a threshold X, and aconstant voltage source SY outputting a threshold Y, as is the case withthe control section 21 (FIG. 15) according to the third embodiment.

In addition, the control section 23 has a variable resistor RX providedbetween the pMOS1 and the pMOS2, a variable resistor RY provided betweenthe nMOS1 and the nMOS2, a differential amplifier AX that compares aninput voltage and the threshold X and outputs a signal for controlling aresistance value of the variable resistor RX, a differential amplifierAY that compares an input voltage and the threshold Y and outputs asignal for controlling a resistance value of the variable resistor SY.

Specifically, the differential amplifier AX outputs a resistance controlsignal to the variable resistor RX so that the larger the differencebetween the input voltage and the threshold X is, the lower theresistance of the variable resistor RX becomes. Because of this, thelarger the difference between the input voltage and the threshold X is,the more swiftly an electric charge is transferred to the capacitor Cpfrom the voltage source. On the contrary, the differential amplifier AYoutputs a resistance control signal to the variable resistor RY so thatthe larger the difference between the input voltage and the threshold Yis, the lower the resistance of the variable resistor becomes. Becauseof this, the larger the difference between the input voltage and thethreshold Y is, the more swiftly an electric charge is transferred tothe earth ground from the capacitor Cp.

Therefore, according to the control section 23, there is provided anintegrator that is able to change a change rate of the control signal.Namely, the control section 23 is capable of increasing a change rate ofthe control signal (the voltage across the terminals of the capacity Cp)when the input voltage is far from the thresholds X and Y and reducing achange rate of the control signal when the input signal is in thevicinity of the threshold. Therefore, an optimal value of the reactancecan be determined in a shorter time and thereby a stable control isrealized.

A Fifth Embodiment

FIG. 18 is a schematic diagram illustrating a control portion 230suitable for a transceiver according to a fifth embodiment of thepresent invention. The control section 230 has a pMOS1, a pMOS2, annMOS1, an nMOS2, a capacitor Cp, a constant voltage source outputting aconstant voltage V1, and a constant voltage source outputting a constantvoltage V2, as is the case with the control section 21 (FIG. 15)according to the third embodiment.

In addition, the control section 230 has a third constant voltage sourceoutputting a constant voltage V3 lower than the constant voltage V1, acurrent source 250 connected between the pMOS1 and the pMOS2, anelectric signal comparator 223 that compares an input voltage and theconstant voltage V3 and outputs a current control signal to the currentsource 250 to cause the current source 250 to flow a first constantcurrent when the input voltage is lower than the constant voltage V3 anda current control signal to the current source 250 to cause the currentsource 250 to flow a second constant current smaller than the secondconstant current when the input voltage is higher than the constantvoltage V3 and lower than the constant voltage V1, a constant voltagesource outputting a constant voltage V4 higher than the constant voltageV2, a current source 226 connected between the nMOS1 and the nMOS2, anda fourth electric signal comparator 224 that compares the input signaland the constant voltage V4 and outputs a current control signal to thecurrent source 226 to cause the current source 226 to flow a thirdconstant current when the input voltage is higher than the constantvoltage V4 and to cause the current source 226 to flow a fourth constantcurrent smaller than the third constant current when the input voltageis higher than the constant voltage V2 and lower than the constantvoltage V4.

The control section 230 having the above configuration operates in thefollowing manner. When the input voltage is lower than the constantvoltage V3, i.e., when the input voltage deviates largely from theconstant voltage V1, the electric signal comparator 223 outputs acurrent control signal to the current source 250 so that the currentsource 250 flows the first constant current to the pMOS2. When the inputvoltage is higher than the constant voltage V3 and lower than theconstant voltage V1, i.e., when the input voltage deviates slightly fromthe constant voltage V1, the electric signal comparator 223 outputs acurrent control signal to the current source 250 so that the currentsource 250 flows the second constant current to pMOS2. Here, the firstconstant current is larger than the second constant current. Therefore,when there is a larger deviation between the input voltage and theconstant voltage V1, a larger current flows from the current source 250,thereby charging the capacitor Cp in a shorter time. In addition, theelectric signal comparator 224 and the current source 226 cooperativelyoperate in the same manner as above.

Therefore, according to the control section 230, when the input voltagedeviates away from the constant voltage V1 or the constant voltage V2,the control signal (the voltage across the capacitor Cp) can change at ahigher rate. When the input voltage is close to the constant voltage V1or the constant voltage V2, the control signal can change at a lowerrate. Therefore, the reactance is optimized in a shorter period and ahigh stability is realized.

By the way, a variable current source can be used instead of the currentsources 225 and 226. In this case, the electric signal comparators 224and 226 are configured so as to output a current control signal to thevariable current source so that the larger the deviation between theinput voltage and the constant voltage V1 or the constant voltage V2 is,the larger the current flows from the variable current source. Forexample, the electric signal comparators 224 and 226 are preferably adifferential amplifier. This can make it possible that when the inputvoltage deviates largely from the constant voltage, a larger current canflow, thereby changing the output voltage swiftly. Also, when thedeviation is small, a smaller current can flow, thereby changing theoutput voltage slowly. Therefore, the reactance is adjusted stably in ashort period.

A Sixth Embodiment

FIG. 19 is a schematic diagram illustrating a configuration of atransceiver according to a sixth embodiment of the present invention.The transceiver according to the sixth embodiment uses a samplingcircuit 24 in order to detect an amplitude of an electric signaldetected by an electric field detection optical section 15 via areceiving-and-transmitting electrode 123. When configuring thetransceiver with an integrated circuit (IC) device, a use of a filterthat requires a large electro static capacity leads to a larger area ofthe IC device, thereby increasing a cost of the IC device. From thispoint of view, a detection method without a use of the filter ispreferable.

In this embodiment, the amplitude is detected by the sampling circuit24. When the sampling circuit detects the amplitude, since a samplingperiod needs to coincide with the period of an electric field induced ina living body, an adjusting signal 13 producing a sampling signal has toreceive a signal from an oscillator 5.

FIG. 20 illustrates a waveform outputted from each component at the timeof reactance adjustment in the transceiver of this embodiment. Into thesampling circuit 24 is inputted a sampling signal in synchronizationwith the peak of a sine wave. The capacitor C1 stores a signal obtainedby sampling the output of a signal processing section 16 when areactance is large, while the capacitor C2 stores the signal when areactance is small. A difference between the stored charges by thecapacitors C1 and C2 is determined by a differential detector 22 andinputted to a control section 21. The control section 21 then outputs acontrol signal based on the output signal from the differential detector22. With this configuration, the amplitude is detected without using afilter.

A Seventh Embodiment

FIG. 21 is a block diagram of a transceiver according to a seventhinvention of the present invention. The transceiver according to theseventh embodiment uses a peak-hold circuit 25 in order to detect theamplitude of an electric signal detected by an electric field detectionoptical section 15 via a receiving-and-transmitting electrode 123.Namely, while the sampling circuit 24 is used to detect the amplitude inthe transceiver according to the sixth embodiment described above, it isthe peak-hold circuit 25 that is used instead in the seventh embodiment.Whereas the sampling circuit 24 requires that the sampling signal has tobe in synchronization with the wave peak, the peak-hold circuit 25 doesnot require such synchronization since the circuit 25 maintains a peakof the signal inputted in a certain period of time when the period isset appropriately long. Therefore, compared with a use of the samplingcircuit 24, the peak-hold circuit 25 affords a larger phase differencebetween a carrier and a signal that drives the peak-hold circuit 25.FIG. 22 illustrates a configuration example of the peak-hold circuit 25.The peak-hold circuit 25 illustrated in FIG. 22 is comprised of a switchSWD1 that turns on in order to input a signal when a detector drivingsignal is at a high level, a capacitor Cpk for holing a peak of an inputsignal, and a switch SWD2 for resetting a reset signal held by thecapacitor Cpk.

FIG. 23 illustrates a waveform of a signal outputted from eachcomponent. In the peak-hold circuit 25, when the drive signal for adifferential detector 22 is at a high level and the reset signal is at alow level, the peak value of the input waveform is stored in thecapacitor Cpk. When the reset signal is at a low level, the electriccharge stored in the capacitor Cpk is discharged, thereby returning tothe initial state. This is performed at the time of the reactance beingboth high and low, thereby storing electric signals representative ofthe amplitude in the capacitors C1 and C2. The difference between thestored electric signals are obtained by the differential detector 22 andintegrated in the control section 21 to output a control signal. By suchan operation, reactance control using the peak-hold circuit 25 isrealized.

An Eighth Embodiment

FIG. 24 is a block diagram of an eighth embodiment of the presentinvention. A transceiver illustrated in FIG. 24 uses apeak-hold/adder-circuit 26 in order to detect an amplitude of anelectric signal detected by an electric field detection optical section15 via a receiving-and-transmitting electrode 123. In addition, FIG. 25illustrates a detailed configuration of the peak-hold/adder-circuit 26,in which there are shown a switch SWD4 that connects a contact a5 and acontact b5 when adding or otherwise connects the contact a5 and acontact c5 in order to maintain the signal, and a switch SWD3 that turnson when resetting the output of an integrator.

In the transceiver of which configuration is illustrated in FIGS. 24 and25, after detection by the peak-hold circuit 27 shown in FIG. 25, anintegrator 28 performs adding at the next stage. Even when a peakexceeds its original amplitude by a sudden noise, a peak-hold circuitholds the peak. Since this may cause an erroneous operation, the peak isdetected several times to be added and then stored in the capacitors C1and C2 in order to alleviate the effect due to noises in thisembodiment.

FIG. 26 illustrates a signal outputted from each component duringreactance adjustment. Firstly, reset signals Q and R are at a low level,and the switches SWD2 and SWD3 are off. In addition, a contact a5 and acontact c5 are connected in the switch SWD4. When the detection drivesignal is at a high level, a signal is inputted into the peak-holdcircuit 27, thereby holding the peak of the input waveform. Then, theinput signal (addition signal) to the switch SWD4 turns to be at a highlevel; the signal maintained at the peak-hold circuit 27 is inputted tothe integrator 28 and added; and the stored signal becomes zero byturning on the switch SWD 2. After this procedure is repeated severaltimes, the capacitor C1 stores the added signal representative of theamplitude when the reactance value is large. Next, after the reactanceis turned to be lower, the same procedure is performed to store theadded signal at the capacitor C2. Next, a signal obtained by taking thedifference using the differential detector 22 is inputted to a controlsection and the control signal is outputted to the variable reactancesection 7. Such a procedure alleviates the effect caused by noise whenperforming reactance adjustment.

A Ninth Embodiment

Referring to FIG. 27, a transceiver according to a ninth embodiment ofthe present invention will be described. In each embodiment describedabove, an electric field induced in the living body is converted into anelectric signal exclusively by the electric field detection opticalsection. The electric signal is supplied either to a signal outputsection when adjusting reactance or to an I/O circuit via a demodulatorsection when receiving the signal to be transmitted by switching. On theother hand, the transceiver according to this embodiment uses dedicatedreceiving sections each for adjusting reactance and for receiving andtransmitting. The transceiver according to this embodiment hassubstantially the same configuration except for the difference in thereceiving section and operates in the same manner as the transceiveraccording to the first embodiment.

Specifically, the transceiver according to this embodiment is providedwith a pre-stage processing section 31 between atransmitting-and-receiving electrode 123 and a detector 8 and also areceiving section 32 between the transmitting-and-receiving electrode123 and an I/O circuit 122 as shown in FIG. 27. The transceiver is notprovided with a switch corresponding to the switch 1 illustrated forexample in FIG. 5. Therefore, a signal to be served for reactanceadjustment is supplied to a signal generation section via the pre-stageprocessing section 31 and a signal to be received is supplied to acomputer via the receiving section 32.

More specifically, the pre-stage processing section 31 includes a filter311 having a high input impedance, an electric field detection section312 converting an electric field into an electric signal, a signalprocessing section 313 having a filter to eliminate noises from theelectric signal. Since the filter 311 is provided at a pre-stage of theelectric field detection section 312, an adverse effect exercised uponresonance is mitigated; noises are eliminated; and a signal processingis facilitated in the post-posed detector 8.

In addition, the receiving section 32 includes an electric fielddetection section 321 converting an electric field in the living bodyinto an electric signal, a signal processing section 322 having a filterfor eliminating noises, an amplifier 323 amplifying the signal fromwhich noises are eliminated, a demodulation circuit 324 demodulating asignal to be received in the electric signal concerned, and a waveformshaper 325 shaping a waveform of a modulated signal. With this, a signalto be received that has been included in the electric field in theliving body 121 is supplied to a computer via the an I/O circuit 122.

As stated above, the transceiver according to the ninth embodiment isprovided with distinct receiving sections each for adjusting reactanceand for receiving/transmitting. Since the pre-stage receiving sectionthat is exclusively used for adjusting reactance is provided with thehigh input impedance filter, reactance adjustment is assuredly andstably performed.

By the way, if the receiving section 32 is not provided in the ninthembodiment, the transceiver concerned can be used as a transmitter thatperforms transmission only.

A Tenth Embodiment

Next, referring to FIG. 28, a transceiver according to a tenthembodiment will be described. As shown in FIG. 28, this transceiver isdifferent from the transceiver according to the ninth embodiment in thata receiving section 32 is provided between a switch 2 and an I/O circuit122. Except for this, the transceiver according to the tenth embodimentshares the same components as the transceiver according to the ninthembodiment.

In the transceiver according to this embodiment, a switch 2 has contactsa1, b1 and c1. When reactance is adjusted or a signal is transmitted,the contacts a1 and b1 are connected. Therefore, a signal suitably usedfor reactance adjustment or a signal including information to betransmitted is supplied to a transmitting-and-receiving electrode 123from an oscillator 5 and a modulation circuit via a variable reactancesection 7. During reception, the contacts b1 and c1 of the switch 2 areconnected and the electric field in the living body is received by thereceiving section 32 via the switch 2. By the way, during reception, acontrol signal is inputted to the variable reactance section 7 so as toreduce the reactance value of the variable reactance section 7.

According to the above configuration, when adjusting reactance ortransmitting, since the receiving section 32 is separated from the othercircuit elements, an influence exercised on the reactance adjustingoperation by the receiving section, specifically, the input stage of thereceiving section, is mitigated. Generally, when adjusting reactance, ahigh voltage is generated due to resonance. When the high voltage has ahigher voltage value than a withstand voltage, the electric circuitconcerned may be damaged. However, according to the above configuration,since the receiving section 32 is separated when adjusting reactance andsuch a high voltage is not applied to the receiving section. Thus, theelectric circuit of the receiving section is prevented from beingdamaged. Therefore, the transceiver according to this embodiment isadvantageous in that a reliability is improved.

By the way, there can be provided a mechanically operable switch betweenthe receiving section 32 and the transmitting-and-receiving electrode123 instead of the switch 2, wherein the mechanically operable switch isoff when adjusting reactance and is on when transmitting. This caneliminate a possibility of damaging the electric circuit of the electriccircuit. By the way, as such a switch, a switch fabricated by micromachine technique, for example, is preferable.

Referring to several embodiments and modifications, a reactanceadjusting apparatus, a transmitter and a communication apparatus usingthe same, and a signal processing circuit according to the presentinvention have been described as above. However, the present inventionis not limited to the above embodiments and modifications and thusvarious alterations are possible.

For example, the signal processing circuit according to modifications ofthe first embodiment is applicable to electric appliances other than thereactance adjusting apparatus.

FIG. 29 is a block diagram illustrating an outlined configuration of anamplifier circuit to which any one of the signal processing circuits100, 200, and 203 described in the above embodiment is applicable. Anamplifier circuit 150 illustrated in FIG. 29 has a function ofautomatically adjusting a gain of the amplifier by a negative feedbackcircuit and any of the above mentioned signal processing circuits isused as a control signal generation means.

A configuration of the amplifier circuit 150 will be described. Theamplifier circuit 150 is comprised of a variable gain amplifier 251 thatis able to change a gain thereof so as to keep constant an amplitude ofan alternating signal outputted even when an amplitude of an inputtedalternating signal is changed, a detector 252 that inputs and detectsthe signal outputted from the variable gain amplifier 251, a filter 253smoothing the signal outputted from the detector 252, a reference signalsource 254 outputting a reference signal to be a target amplitude of thesignal outputted from the variable gain amplifier 251, a comparator 255comparing the signal outputted from the filter 253, the signalcorresponding to the amplitude of the signal from the variable gainamplifier 251, and the signal outputted from the reference signal source254 to determine the difference between the two signals, and anintegrator 256 outputting a control signal based on the integrationresult. Nothing to say that any one of the signal processing circuits100, 200, and 203 is applicable as the integrator 256.

In the amplifier circuit 150 having the above configuration, when thesignal outputted from the filter 253 is higher than the referencesignal, the signal outputted from the integrator 256, i.e., the controlsignal controlling the gain of the variable gain amplifier 251 becomeslarge. As a result, the gain of the variable gain amplifier 251 becomeslarge accordingly. On the other hand, when the signal outputted from thefilter 253 is lower than the reference signal, the signal (controlsignal) outputted from the integrator 256 becomes small, therebyreducing the gain of the variable gain amplifier 251. Such a signalprocessing continues until the signal outputted from the filter 253,which corresponds to the amplitude of the signal outputted from thevariable gain amplifier 251, becomes equal to the reference signal (atarget value). The amplitude of the signal outputted from the variablegain amplifier 251 is kept constant even when the amplitude of thealternating signal to be inputted to the variable gain amplifier 251 isvaried.

In the amplifier circuit 150 having such a function, even a coincidenceof an observed value with the target value does not lead to an unstablestate. Therefore, no large current flows from a voltage source Vdd tothe earth ground, thereby preventing an energy consumption fromincreasing.

By the way, each of the above-stated signal processing circuits 100,200, and 203 is only an embodiment of the signal processing circuitaccording to the present invention and the signal processing circuitapplicable as the integrator 256 is not limited to the embodiments.Namely, the present invention includes various embodiments that exertsubstantially the same operation and effect as the signal processingcircuits 100, 200 and 203, without departing from the scope and spiritof the claims. A use of such embodiments makes it possible to configurethe amplifier circuit 150 according to the above example.

INDUSTRIAL APPLICABILITY

A reactance adjuster, a transceiver, a transmitting apparatus, and asignal processing circuit preferable for these are preferably applicablefor example to a wearable computer system mountable to a human body.

1. A reactance adjuster for adjusting reactance caused by acommunication apparatus that transmits and/or receives a signal via anelectric field transmittable medium (121) and said electric fieldtransmittable medium (121), a signal generation section (5, 6)generating a probe signal, an electrode (123) inducing an electric fieldbased on said probe signal in said electric field transmittable medium(121), a resonance section (7) that is connected between said signalgeneration section (5, 6) and said electrode (123) and induces a seriesresonance by adjusting reactance against parasitic capacitance inducedbetween said electric field transmittable medium (123), saidcommunication apparatus, and an earth ground, an adjusting signalgeneration section (13) outputting alternatingly a high level signal anda low level signal to said resonator section (7), an electric fielddetection section (15) that receives an electric field in said electricfield transmittable medium (121) and generates an electric signal basedon the received electric field, a signal output section including afirst electric charge storing means (C1) storing an electric charge inaccordance with said electric signal while said adjusting signalgeneration section (13) outputs a high level signal to said resonatorsection (7), a second electric charge storing means (C2) storing anelectric charge in accordance with said electric signal while saidadjusting signal generation section (13) outputs a low level signal tosaid resonator section (7), and a voltage comparator (10) comparing avoltage across said first electric charge storing means (C1) and avoltage across said second electric charge storing means (C2) to outputa predetermined signal in accordance with the comparison result, and acontrol section (19; 20; 21; 23; 230) that outputs a voltage having aconstant voltage value to said resonator section (7) while either one ofsaid first and said second electric charge storing means (C1, C2) isstoring an electric charge, and inputs said predetermined signal tooutput a voltage based on the inputted predetermined signal to saidresonator section (7) while said first and second electric chargestoring means stop storing an electric charge.
 2. A reactance adjusteras recited in claim 1, wherein said control section (19) comprises: aconstant voltage source (12) outputting the voltage having apredetermined voltage value, an integrator (11; 100; 200; 203)outputting a voltage having said constant voltage value when receivingthe voltage having said predetermined voltage value and outputting avoltage based on said predetermined signal when receiving saidpredetermined voltage to said resonator section (7), an output switchingsection (4) inputting selectively the voltage having said predeterminedvoltage value or said predetermined signal, thus outputting said voltagehaving said predetermined voltage value to said integrator (11) whileeither one of said first and said second electric charge storing means(C1, C2) is storing an electric charge and outputting said predeterminedsignal to said integrator (11) when said first and second electriccharge storing means stop storing an electric charge.
 3. A reactanceadjuster as recited in claim 2, wherein said integrator (100) comprises:a first connection means (SW1), one end of which is connected to apositive electrode of a voltage source (Vdd) outputting a predeterminedvoltage, a second connection means (SW2), one end of which is connectedto the other end of said first connection means (SW1) and the other endof which is connected to a negative electrode of said voltage source, afirst comparison means (211; 221; 231) comparing a predetermined firstthreshold voltage (V1) and said predetermined signal to output a signalfor turning on said first connection means (SW1) when said predeterminedsignal is lower than said first threshold voltage (V1), a secondcomparison means (212; 222; 232) comparing a second threshold voltage(V2) higher than said first threshold voltage (V1) and saidpredetermined signal to output a signal for turning on said connectionmeans (SW2) when said predetermined signal is higher than said secondthreshold voltage (V2), and a capacitor (213; 227; 237), one end ofwhich is connected to said other end of said first connection means andthe other end of which is connected to said negative electrode.
 4. Areactance adjuster as recited in claim 3, wherein said integrator (200)further comprises: a first current source (225) provided between saidpositive electrode and said first connection means (SW1), a thirdcomparison means (223) that compares said predetermined signal and athird threshold voltage (V3) lower than said first threshold voltage(V1) and outputs a current control signal to said first current source(225) so that a first constant current having a predetermined currentvalue flows from said first current source (225) when said predeterminedsignal is lower than said threshold voltage (V3) or a second constantcurrent smaller than said first constant current flows from said firstcurrent source (225) when said predetermined signal is higher than saidthird threshold voltage (V3) and lower than said first threshold voltage(V1), a second current source (236) provided between said negativeelectrode and said second connection means, and a fourth comparisonmeans (224) that compares said predetermined signal and said fourththreshold voltage (V4) higher than said second threshold voltage (V2)and outputs a current control signal to said second current source (236)so that a third constant current flows from said second current source(236) when said predetermined signal is higher than said fourththreshold voltage or a fourth current smaller than said third currentflows from said second current source (236) when said predeterminedsignal is higher than said second threshold voltage (V2) and lower thansaid fourth threshold voltage (V4).
 5. A reactance adjuster as recitedin claim 3, wherein said integrator (203) further comprises: a firstvariable current source (235) provided between said positive electrodeand said first connection means (SW1), a first differential amplifyingmeans (233) that compares said predetermined signal and said firstthreshold voltage (V1) and outputs a current control signal to saidfirst variable current source (235) so that the smaller said determinedsignal is, the larger the current flows from said variable currentsource (235), a second variable current source (236) provided betweensaid negative electrode and said second connection means (SW2), and asecond differential amplifying means (234) that compares saidpredetermined signal and said second threshold voltage (V2) and outputsa current control signal to said second variable current source (236) sothat the higher said predetermined signal is, the larger the currentflows from said second variable current source (236).
 6. A reactanceadjuster as recited in claim 3, wherein said integrator furthercomprises: a first variable resistor provided between said positiveelectrode and said first connection means (SW1), a first differentialamplifying means that compares said predetermined signal and said firstthreshold voltage and outputs a resistance value control signal to saidfirst variable resistor so that the lower said predetermined signal is,the lower the resistance of said first variable resistor becomes, asecond variable resistor provided between said negative electrode andsaid second connection means, and a second differential amplifying meansthat compares said predetermined signal and said second thresholdvoltage and outputs a resistance value control signal to said secondvariable resistor so that the higher said predetermined signal is, thelower the resistance of said second variable resistor becomes.
 7. Areactance adjuster as recited in claim 1, wherein said control section(20) comprises: a first p-channel Metal Oxide Semiconductor Field EffectTransistor (MOS-FET) (pMOS1) that turns off while either one of saidfirst and said second electric charge storing means (C1, C2) is storingan electric charge and turns on when said first and said second electriccharge storing means (C1, C2) stop storing, a second p-channel MOS-FET(pMOS2) connected in series with said first p-channel MOS-FET (pMOS1),said second p-channel MOS-FET (pMOS2) turning on when said voltagecomparator (10) determines that a voltage across said first electriccharge storing means (C1) is higher than a voltage across said secondelectric charge storing means (C2) and turning off when said voltagecomparator (10) determines that a voltage across said first electriccharge storing means (C1) is lower than a voltage across said secondelectric charge storing means (C2), a first n-channel MOS-FET (nMOS1)connected in series with said second p-channel MOS-FET (pMOS2), saidfirst n-channel MOS-FET (nMOS1) turning on when said voltage comparator(10) determines that a voltage across said first electric charge storingmeans (C1) is lower than a voltage across said second electric chargestoring means (C2) and turning off when said voltage comparator (10)determines that a voltage across said first electric charge storingmeans (C1) is higher than a voltage across said second electric chargestoring means (C2), a second n-channel MOS-FET (nMOS2) connected inseries with said first n-channel MOS-FET (nMOS1), said second n-channelMOS-FET (nMOS2) turning off when either one of said first and saidsecond electric charge storing means (C1, C2) is storing an electriccharge and turning on when said first and said second electric chargestoring means (C1, C2) stop storing, and a capacitor (Cp), one end ofwhich is connected to a node between said second p-channel MOS-FET(pMOS2) and said first n-channel MOS-FET (nMOS1) and the other end ofwhich is connected to the earth ground.
 8. A reactance adjuster asrecited in claim 7, wherein said control section (21) further comprises:a first reference voltage source (SX) outputs a predetermined firstreference voltage, a first voltage comparator (X) comparing saidpredetermined signal and said first reference voltage to output avoltage in accordance with the comparison result to said secondp-channel MOS-FET (pMOS2), a second reference voltage source outputtinga predetermined second reference voltage, and a second voltagecomparator (Y) comparing said predetermined signal and said secondreference voltage to output a voltage in accordance with the comparisonresult to said first n-channel MOS-FET (nMOS1).
 9. A reactance adjusteras recited in claim 8, wherein said control section (23) furthercomprises: a first variable resistor (RX) connected between said firstp-channel MOS-FET (pMOS1) and said second p-channel MOS-FET (pMOS2), athird comparator comparing said first reference voltage and saidpredetermined signal to output a signal in accordance with thecomparison result so as to control resistance of said first variableresistor (RX), a second variable resistor (RY) connected between saidfirst n-channel MOS-FET (nMOS1) and said second n-channel MOS-FET(nMOS2), and a fourth comparator (AY) comparing said second referencevoltage and said predetermined signal to output a signal in accordancewith the comparison result so as to control resistance of said secondvariable resistor (RY).
 10. A reactance adjuster as recited in claim 8,wherein said control section (230) further comprises: a first currentsource (250) connected between said first p-channel MOS-FET (pMOS1) andsaid second p-channel MOS-FET (pMOS2), a third signal comparison means(223) that compares said predetermined signal and a third referencevoltage lower than said first reference voltage and outputs a currentcontrol signal to said first current source (250) so that said firstcurrent source (250) flows a first constant current when saidpredetermined signal is lower than said third reference voltage or saidfirst current source (250) flows a second constant current smaller thansaid first constant current when said predetermined signal is higherthan said third reference voltage and lower than said first referencevoltage, a second current source (226) connected between said firstn-channel MOS-FET (nMOS1) and said second n-channel MOS-FET (nMOS2), anda fourth signal comparator (224) that compares said predetermined signaland a fourth reference voltage higher than said second reference voltageand outputs a current control signal to said second current source (226)so that said second current source (226) flows a third constant currentwhen said predetermined signal is higher than said fourth referencevoltage or said second current source (226) flows a fourth constantcurrent smaller than said third constant current when said predeterminedsignal is higher than said second reference voltage and lower than saidfourth reference voltage.
 11. A reactance adjuster as recited in eitherclaim 4 or 10, wherein said first constant current and said thirdconstant current have a same current value, and wherein said secondconstant current and said fourth constant current have a same currentvalue.
 12. A reactance adjuster as recited in claim 8, wherein saidcontrol section (21) further comprises: a first variable current sourceconnected between said first p-channel MOS-FET (pMOS1) and said secondp-channel MOS-FET (pMOS2), a first differential amplifying meanscomparing said predetermined signal and said first reference voltage tooutput a current control signal to said first variable current source sothat the smaller said predetermined signal is, the larger the currentflows from said first variable current source, a second variable currentsource connected between said first n-channel MOS-FET (nMOS1) and saidsecond n-channel MOS-FET (nMOS2), and a second differential amplifyingmeans comparing said predetermined signal and said second referencevoltage to output a current control signal to said second variablecurrent source so that the larger said predetermined signal is, thelarger the current flows from said second variable current source.
 13. Areactance adjuster as recited in claim 1, wherein said signal outputsection further comprises a detection means (8) detecting an amplitudeof said electric signal to output a detection voltage in accordance withsaid amplitude, and a filter (9) eliminating a high harmonics componentfrom said detection voltage.
 14. A reactance adjuster as recited inclaim 1, wherein said signal output section further comprises a samplingmeans (25) sampling said electric signal to output a voltage inaccordance with said electric signal.
 15. A reactance adjuster asrecited in claim 1, wherein said signal output section further comprisesa peak-hold means (25) holding a peak value of an amplitude of saidelectric signal to output a voltage in accordance with the peak value.16. A reactance adjuster as recited in claim 15, wherein said peak-holdmeans (26) comprises an addition means (26) detecting said peak value ata predetermined number of times to add said peak value.
 17. A reactanceadjuster as recited as any one of claims 1 to 16, wherein said controlsection (19; 20; 21; 23; 230) further comprises an adder (14) adding avoltage based on a voltage having said constant voltage value outputtedto said resonance section (7) from said control section (19; 20; 21; 23;230) or a voltage based on said predetermined signal and a high levelsignal or a low level signal being alternatingly outputted to saidresonance section (7) from said adjusting signal generation section(13).
 18. A signal processing circuit comprising: a first connectionmeans (SW1), one end of which is connected to a positive electrode of avoltage source (Vdd) outputting a predetermined voltage, a secondconnection means (SW2), one end of which is connected to the other endof said first connection means (SW1) and the other end of which isconnected to a negative electrode of said voltage source, a firstcomparison means (211) that compares a predetermined first thresholdvoltage (V1) and an input voltage and outputs a signal to turn on saidfirst connection means (SW1) when said input voltage is lower than saidfirst threshold voltage (V1), a second comparison means (212) thatcompares an input voltage and a second threshold voltage (V2) higherthan said first threshold voltage (V1) and outputs a signal to turn onsaid second connection means (SW2) when said input voltage is higherthan said second threshold voltage (V2), and a capacitor (213), one endof which is connected to said other end of said connection means (SW1)and the other end of which is connected to said negative electrodes. 19.A signal processing circuit as recited in claim 18, further comprising:a first current source (225) provided between said positive electrodeand said first connection means (SW1), a third comparison means (223)that compares an input voltage and a third threshold voltage (V3) lowerthan said first threshold voltage (V1) and output a current controlsignal to said first current source (225) so that a first constantcurrent flows from said first current source (225) when said inputvoltage is lower than said third threshold voltage (V3) or a secondconstant current smaller than said first constant current flows fromsaid first current source (225) when said input voltage is higher thansaid third threshold voltage (V3) and lower than said first thresholdvoltage, a second current source (226) provided between said negativeelectrode and said second connection means (SW2), and a fourthcomparison means (224) that compares an input voltage and a fourththreshold voltage (V4) higher than said second threshold voltage (V2)and outputs a current control signal to said second current source (226)so that a third constant current flows from said second current source(226) when said input voltage is higher than said fourth thresholdvoltage (V4) or a fourth constant current smaller than said thirdconstant current flows from said second current source (226) when saidinput voltage is higher than said second threshold voltage (V2) andlower than said fourth threshold voltage (V4).
 20. A signal processingcircuit as recited in claim 18, further comprising: a first variablecurrent source (235) provided between said positive electrode and saidfirst connection means (SW1), a first differential amplifying means(233) that compares an input voltage and said first threshold voltage(V1) and outputs a current control signal to said first variable currentsource (235) so that the lower said input voltage is, the larger thecurrent flows from said first variable current source (235), a secondvariable current source (236) provided between said negative electrodeand said second connection means (SW2), and a second differentialamplifying means (234) that compares an input voltage and said secondthreshold voltage (V2) and outputs a current control signal to saidsecond variable current source (236) so that the higher said inputvoltage is, the larger the current flows from said second variablecurrent source (236).
 21. A signal processing circuit as recited inclaim 18, further comprising: a first variable resistor provided betweensaid positive electrode and said first connection means (SW1), a firstdifferential amplifying means that compares an input voltage and saidfirst threshold voltage and outputs a resistance control signal to saidfirst variable resistor so that the lower said input voltage is, thesmaller the resistance of said first variable resistor becomes, a secondvariable resistor provided between said negative electrode and saidsecond connection means, and a second differential amplifying means thatcompares an input voltage and said second threshold voltage and outputsa resistance control signal to said second variable resistor so that thehigher said input voltage is, the lower the resistance of said secondvariable resistor becomes.
 22. A transceiver transmitting and receivingdata via an electric field transmittable medium, comprising: a reactanceadjuster as recited in any one of claims 1 to 17, an interface portion(122) for use in communication with a computer managing data to betransmitted, a data signal generation portion provided between saidinterface portion (122) and said resonance portion, said data signalgeneration portion generating a signal wave including data to betransmitted obtained via said interface portion (122) to supply the datato said resonance portion (7), and a receiving portion (32) providedbetween said interface portion (122) and said electrode (123), saidreceiving portion (32) detecting an electric field in said electricfield transmittable medium via said electrode (123) and obtaining datato be received from the electric field detected so as to supply the datato said interface portion (122).
 23. A transceiver as recited in claim22, wherein said receiving portion (32) inputs a converted electricsignal from said electric field detection portion (15) and obtains datato be received from the electric signal to supply to said interfaceportion (122).
 24. A transceiver as recited in any one of claims 22 and23, wherein said data signal generation portion generates said probesignal.
 25. A transmitter transmitting data via an electric fieldtransmittable medium (121), comprising: a reactance adjuster as recitedin any one of claims 1 to 17, an interface portion (122) for use incommunication with a computer managing data to be transmitted, and adata signal generation portion provided said interface portion (122) andsaid resonance portion, said data signal generation portion generating asignal wave including data to be transmitted obtained via said interfaceportion (122) to supply to said resonance portion (7).
 26. A transmitteras recited in claim 26, wherein said data signal generation portiongenerates said probing signal.
 27. A method of adjusting reactancecaused by a communication apparatus transmitting/receiving data via anelectric field transmittable medium (121) and said electric fieldtransmittable medium, said method comprising: inducing an electric fieldbased on a probe signal generated from a signal generation portion (5,6) in said electric field transmittable medium (121) via an electrode(123), outputting alternatingly a high level signal and a low levelsignal to a resonance portion (7) generating a series resonance byadjusting a reactance value against parasitic capacitance caused betweensaid electric field transmittable medium (121), a communicationapparatus, and an earth ground, said resonance portion (7) beingconnected in series between said signal generation portion (5, 6) andsaid electrode (123), receiving the electric field in said electricfield transmittable medium (121) via said electrode (123), generating anelectric signal based on the received electric field, storing anelectric charge based on said electric signal in a first electric chargestoring means (C1) when outputting a high level signal to said resonanceportion (7), storing an electric charge based on said electric signal ina second electric charge storing means (C2) when outputting a low levelsignal to said resonance portion (7), and outputting a predeterminedsignal based on a voltage difference between a voltage across said firstelectric charge storing means (C1) and a voltage across said secondelectric charge storing means (C2), and outputting a voltage having aconstant voltage value to said resonance portion (7) when either one ofsaid first electric charge storing means (C1) and said second electriccharge storing means (C2) is storing electric charge and outputting avoltage based on said predetermined signal to said resonance portion (7)when said first electric charge storing means (C1) and said secondelectric charge storing means (C2) stop storing.
 28. A method oftransmitting signal via an electric field transmittable medium (121),comprising: inducing an electric field based on a probe signal generatedfrom a signal generation portion (5, 6) in said electric fieldtransmittable medium (121) via an electrode (123), outputtingalternatingly a high level signal and a low level signal to a resonanceportion (7) generating a series resonance by adjusting a reactance valueagainst parasitic capacitance caused between said electric fieldtransmittable medium (121), a communication apparatus, and an earthground, said resonance portion (7) being connected in series betweensaid signal generation portion (5, 6) and said electrode (123),receiving an electric field in said electric field transmittable medium(123) via said electrode (123), generating an electric signal based onthe received electric field, storing an electric charge based on saidelectric signal in a first electric charge storing means (C1) whenoutputting a high level signal to said resonance portion (7), storing anelectric charge based on said electric signal in a second electriccharge storing means (C2) when outputting a low level signal to saidresonance portion (7), and outputting a predetermined signal based on avoltage difference between a voltage across said first electric chargestoring means (C1) and a voltage across said second electric chargestoring means (C2), outputting a voltage having a constant voltage valueto said resonance portion (7) when either one of said first and saidsecond electric charge storing means (C1, C2) is storing electric chargeand outputting a voltage based on said predetermined signal when saidfirst and said second electric charge storing means (C1, C2) stopstoring, and supplying a signal wave including data to be transmitted tosaid electrode.
 29. A method of receiving signal via an electric fieldtransmittable medium (121), comprising: inducing an electric field basedon a probe signal generated from a signal generation portion (5, 6) insaid electric field transmittable medium (121) via an electrode (123),outputting alternatingly a high level signal and a low level signal to aresonance portion (7) generating a series resonance by adjusting areactance value against parasitic capacitance caused between saidelectric field transmittable medium (121), a communication apparatus,and an earth ground, said resonance portion (7) being connected inseries between said signal generation portion (5, 6) and said electrode(123), receiving the electric field in said electric field transmittablemedium (121) via said electrode (123), generating an electric signalbased on the received electric field, storing an electric charge basedon said electric signal in a first electric charge storing means (C1)when outputting a high level signal to said resonance portion (7),storing an electric charge based on said electric signal in a secondelectric charge storing means (C2) when outputting a low level signal tosaid resonance portion (7), and outputting a predetermined signal basedon a voltage difference between a voltage across said first electriccharge storing means (C1) and a voltage across said second electriccharge storing means (C2), outputting a voltage having a constantvoltage value to said resonance portion (7) when either one of saidfirst and said second electric charge storing means (C1, C2) is storingelectric charge and outputting a voltage based on said predeterminedsignal when said first and said second electric charge storing means(C1, C2) stop storing, receiving the electric field in said electricfield transmittable medium via said electrode to generate a receivingdata electric signal including data to be received, and demodulatingsaid receiving data electric signal to obtain said data.